New algorithms for faster trace generation are based on EDMD protocol. Copper planes (including internal layers) are also supported. The user can choose to use surface traces or solid traces with thickness so all copper can be visible in CATIA in two ways.
Two algorithms for wires in CATIA are developed:
- Surface wire for quick clearance check and for high density PCB used for thermal simulation
- Solid wire with real wire thickness from PCB layer stack-up definition in ECAD tools used for real 3D simulation