New algorithms for faster trace generation are based on EDMD protocol. Copper planes, including internal layers, are also supported. The user can choose to display copper traces in CATIA in two ways: surface traces or solid traces with thickness.
Two algorithms for wires in CATIA are developed:
- Surface wires for quick clearance checks and for high-density PCBs used for thermal simulation
- Solid wires with real wire thickness from PCB layer stack-up definitions in ECAD tools, used for real 3D simulation.